The present disclosure relates to a semiconductor structure and a method of forming the same. More particularly, the present disclosure relates to a three-dimensional (3D) integrated circuit in which improved Cu-to-Cu bonding is achieved.
To address the scaling requirements of today's electronic devices, chip designers and manufacturers are constantly trying to devise circuit designs that best maximize available chip space. The resulting designs often extend to several different planes. For example, one such three-dimensional (3D) circuit design might involve a number of different device layers oriented in a stacked configuration. In another example, a 3D circuit design might include vertical stacks consisting of multiple device layers and interconnect layers that are connected together by interlayer vertical vias.
In a typically 3D integrated circuit, two active device wafers are stacked in a back-to-back manner. The two active device wafers are then bonded together using thermal compression in which Cu-to-Cu bonding occurs. The bonding process requires both reasonable high temperatures and pressure application. In such direct Cu-to-Cu bonding, CuO forms at the Cu surfaces that are being bonded together. The presence of CuO at the Cu surfaces increases the resistance of the bonded structure and reduces the reliability, particularly, the adhesion, of the bonded structure.
As such, there is a need for an improved method for bonding Cu surfaces together in which the formation of CuO at the bonded Cu-to-Cu surface is eliminated.